Field-Programmable Gate Array

A field-programmable gate array (FPGA) is an integrated circuit whose internal logic and routing are configured after manufacturing by loading a bitstream into on-chip configuration memory. Where an application-specific integrated circuit (ASIC) bakes its function into mask layers at silicon fabrication, an FPGA ships as a sea of generic primitives (look-up tables (LUTs), flip-flops, block RAM, digital signal processing (DSP) slices, input/output (I/O) buffers) connected by a programmable routing fabric; loading a bitstream wires those primitives into whatever circuit the designer described in a hardware description language (Wikipedia: FPGA). The first commercially viable FPGA, the Xilinx XC2064, shipped in 1985 with 64 configurable logic blocks. Modern devices span from sub-dollar hobbyist parts with thousands of LUTs (Lattice iCE40, Gowin LittleBee) to data-center accelerators with millions of LUTs and embedded ARM cores (AMD Versal, Intel Stratix). The definitely-not-esp32 project targets the Sipeed Tang Nano 20K, a Gowin GW2AR-18 with 20,736 LUT4s, which sits comfortably in the hobbyist end of that range.

Mental Model

An FPGA is a programmable patch cable plus a programmable truth table, repeated millions of times on one die. Each configurable logic block holds a few lookup tables (small RAMs that implement arbitrary Boolean functions of k inputs) and flip-flops; each switch box in the routing fabric is a programmable crosspoint that decides which wires connect to which. The bitstream is the union of every LUT’s contents and every switch’s configuration. Once loaded, the device looks (electrically) exactly like the digital circuit the designer wrote, with one unavoidable price: every signal pays for the multiplexers and routing it traverses, so an FPGA implementation of a given circuit is slower and larger than the same circuit as a custom ASIC. The trade is total flexibility for a constant area-and-speed factor.

flowchart TB
  HDL["Verilog / SystemVerilog<br/>VHDL / Chisel"] -->|"synthesis<br/>(Yosys, Vivado, Quartus, Gowin EDA)"| NETLIST["Gate-level netlist<br/>(LUTs, FFs, BRAMs, DSPs)"]
  NETLIST -->|"technology map"| MAPPED["Mapped netlist<br/>(vendor primitives only)"]
  MAPPED -->|"place"| PLACED["Placed: every primitive<br/>assigned a CLB location"]
  PLACED -->|"route"| ROUTED["Routed: every signal<br/>assigned to a wire"]
  ROUTED -->|"timing analysis<br/>(STA)"| TIMING{"meets clock<br/>target?"}
  TIMING -- "no" --> PLACED
  TIMING -- "yes" --> BIT["Bitstream<br/>(.bit / .fs / .bin)"]
  BIT -->|"JTAG / SPI flash"| FPGA["FPGA configuration RAM<br/>(SRAM-based: load on power-up)"]
  FPGA --> RUN["Running circuit"]

The FPGA flow from RTL to running silicon. What it shows: synthesis turns HDL into a generic netlist of logic primitives, technology mapping replaces those with the specific FPGA’s vendor cells (typically 4 to 6 input LUTs), place-and-route assigns each cell to a physical location on the die and routes every signal through the programmable fabric, static timing analysis checks the result against the target clock, and the bitstream encoding of the final configuration is loaded into the device. The insight to take: the long iterative loop is place-and-route plus timing closure, not synthesis itself; this is where multi-hour build times come from on large designs, and the dominant reason FPGA verification happens in software simulation (Verilator) first.

The Building Blocks

Look-Up Tables

The LUT is the FPGA’s universal combinational primitive. A k-input LUT is, electrically, a 2^k-bit SRAM whose address inputs are the k logic inputs and whose data output is the function value. Loading the LUT with a 2^k-bit truth table makes it implement any Boolean function of those k inputs (Wikipedia: Lookup table: “An n-bit LUT can encode any n-input Boolean function by storing the truth table of the function in the LUT”). The historical sweet spot has been k = 4: a 4-LUT (16 bits of state, 4-bit address decoder) is small enough that you can pack many per die while still covering most useful gates and small structures (a full adder fits in two 4-LUTs). Modern Xilinx 7-Series and UltraScale parts use 6-LUTs that can be split into two 5-LUTs sharing four inputs; Gowin’s LittleBee (the Tang Nano 9K’s family) uses 4-LUTs. Lattice iCE40 also uses 4-LUTs (Wikipedia: FPGA).

Flip-Flops

Every LUT typically comes paired with one (or more) D-type flip-flops, the sequential element that holds state across clock cycles. A LUT plus a flip-flop is the logic cell: combinational input transformation followed by an optional register, the unit out of which all synchronous circuits are built. The number of flip-flops on an FPGA is the cap on stateful resources; a CPU pipeline with 32 architectural registers and several deep pipeline buffers easily consumes hundreds of flip-flops just for the register file. The Tang Nano 20K’s GW2AR-18 reports 20,736 LUT4s and 15,552 flip-flops (Sipeed wiki: Tang Nano 20K).

Routing Fabric

The interconnect between logic blocks is the FPGA’s largest physical resource by area (often 80% of the die). It consists of pre-fabricated metal wires of varying lengths (local, longline, global), gated at each crosspoint by a programmable transistor. The bitstream sets every crosspoint to on or off, picking the path each signal takes. The routing fabric is also what makes FPGA timing hard to predict: a small RTL change can re-route a critical path through different long wires, changing the maximum clock frequency by tens of percent. This is why the synthesis flow includes static timing analysis (STA) as a closing step and why “fits but does not meet timing” is the second most common build failure after “does not fit.”

Block RAM and Distributed RAM

Large memories are too expensive to build from flip-flops; FPGAs include dedicated block RAM (BRAM) macros, typically 4 to 36 Kbits each, with configurable widths (1-bit by 16K, 8-bit by 2K, 36-bit by 1K, etc.) and one or two synchronous read/write ports. The Tang Nano 20K’s GW2AR has 46 BRAMs totalling 828 Kbits (Sipeed wiki: Tang Nano 20K), plus 41 Kbits of “shadow SRAM” usable as distributed memory inside the logic fabric. For the definitely-not-esp32 core, BRAM is the resource that holds the boot ROM, the on-chip data RAM, and any caches. Distributed RAM (LUT-RAM), where a LUT is configured as a tiny addressable memory rather than as combinational logic, is faster for small structures like register files and the branch-history table.

DSP Slices

For multiply-heavy workloads (signal processing, neural network inference, the RV32IM MUL family), FPGAs include hardened DSP slices, dedicated multipliers (typically 18 by 18 bit or 25 by 18 bit) with associated accumulators. Implementing multiply in pure LUTs costs hundreds of LUTs per multiplier and runs slowly; a DSP slice runs at hundreds of MHz on the same fabric. The Tang Nano 20K provides 48 DSP multipliers, which is more than ample for the definitely-not-esp32 core’s single integer multiplier.

I/O Buffers

Every device pin connects to a configurable I/O block that supports multiple voltage standards (3.3 V LVCMOS, 1.8 V, LVDS differential pairs), pull-ups, drive strength, and direction (input, output, bidirectional). Hard blocks for high-speed interfaces (PCIe, DDR, multi-gigabit transceivers) appear on larger devices; the small parts used in hobbyist projects expose only single-ended LVCMOS plus a handful of differential pairs.

Synthesis and the Bitstream Pipeline

The flow from RTL to a configured device involves several distinct tools, traditionally vendor-proprietary, increasingly open-source:

Synthesis turns the HDL (Verilog, SystemVerilog, VHDL, or a generator language like Chisel that emits Verilog) into a generic gate-level netlist of AND/OR/NOT/flip-flop primitives (Wikipedia: Logic synthesis). The synthesizer infers structures (a flip-flop from a clocked always_ff block, a multiplier from an * operator, a BRAM from a clocked memory array) and optimizes them. Open-source synthesis is dominated by Yosys; vendor flows use AMD Vivado, Intel Quartus, Lattice Diamond / Radiant, Gowin EDA.

Technology mapping replaces generic gates with the specific FPGA’s primitives: clusters of gates become 4- or 6-LUTs with specific contents; flip-flops become the device’s flip-flop primitive; memory arrays become BRAM instances. The output is a netlist of only vendor cells.

Placement assigns every netlist instance to a physical location on the die. It is an NP-hard optimization that vendor tools attack with simulated annealing and analytic placement. Good placement keeps connected logic physically close to minimize routing delay.

Routing picks the specific wires and switch settings to connect every placed signal to its consumers. Routing is the slowest step of the flow on large designs; congestion (too many signals trying to use too few wires in a region) causes the router to back-track and re-place.

Static timing analysis computes, for every flip-flop-to-flip-flop path, the propagation delay through LUTs and wires, and verifies that the longest path is less than the clock period minus setup time. A design that fits but does not meet timing must be re-pipelined or re-architected.

Bitstream generation encodes every LUT’s truth table, every flip-flop’s reset value, every BRAM’s initial contents, and every switch box setting into the vendor-specific binary format (.bit for Xilinx, .fs for Gowin, .bin for Lattice). The bitstream is loaded into the device by JTAG (for development) or from an attached SPI flash (for deployment).

The end-to-end flow for a small RV32IMC core on the Tang Nano 20K, using Gowin EDA, runs in roughly two to five minutes; on a million-LUT data-center FPGA the same flow takes hours.

SRAM-Based vs Flash-Based vs Antifuse Configuration

The choice of what physical memory holds the bitstream divides the FPGA market.

SRAM-based is dominant. The configuration sits in on-chip SRAM, which is fast and unlimited-write but volatile: power off, lose configuration. The device must reload the bitstream from an external SPI flash (or JTAG) on every power-up. AMD/Xilinx, Intel/Altera, Lattice ECP5, and Gowin Arora are all SRAM-based. Reconfiguration count is unlimited (or rather, bounded only by flash wear in the external boot device, which is millions of cycles).

Flash-based stores the configuration in on-chip flash, which is non-volatile but limited to roughly 100,000 to 1,000,000 program-erase cycles per cell. The device boots instantly with no external memory. Microsemi’s IGLOO, Lattice’s MachXO/iCE40 UltraPlus (which has internal NVCM, a sort of one-time-programmable flash variant), and Gowin’s LittleBee with internal flash are examples. These parts win for low-pin-count systems and for low-power applications that cannot afford a separate flash chip.

Antifuse is one-time programmable, fused at first configuration and never changed. Historically used in radiation-hardened space and military FPGAs (Microsemi RTAX) where SRAM upset by cosmic rays is unacceptable. Mostly obsolete outside specialty markets (Wikipedia: FPGA).

EEPROM and antifuse are now largely superseded by flash and SRAM. For hobbyist work, SRAM with external SPI flash is the universal default; the Tang Nano 20K, for example, includes an on-board 64 Mbit SPI flash that the BL616 microcontroller programs over USB (Sipeed wiki: Tang Nano 20K).

FPGA vs ASIC

The classic comparison: an FPGA implementation of the same design uses substantially more silicon area, more dynamic power, and runs at a fraction of the clock frequency of an ASIC implementation. A 2006 study cited by the Wikipedia FPGA article reported FPGAs requiring “40 times as much area, draw 12 times as much dynamic power, and run at one third the speed” of an equivalent ASIC. Those numbers are dated (the gap narrows with each generation of FPGA, particularly as hardened blocks for common functions absorb area-hungry operations), but the order-of-magnitude relationship still holds.

The FPGA wins on:

• Non-recurring engineering (NRE) cost. An ASIC mask set on a leading-edge node costs tens of millions of dollars; an FPGA development kit costs $25to$5,000.
• Time to first silicon. An FPGA implementation can be compiled and flashed in minutes; an ASIC takes 3 to 12 months to fabricate after design freeze.
• Reprogrammability. Bug fixes after deployment are a bitstream update, not a respin. “It can be reprogrammed in the field to fix bugs or make other improvements” (Wikipedia: FPGA).
• Hardware-software co-development. During prototyping the design can change daily.

The ASIC wins on:

• Unit cost at volume. Above tens of thousands of units, ASIC unit cost drops below FPGA cost by an order of magnitude.
• Performance and power. A custom mask gives every transistor exactly the right size for its job; an FPGA must over-provision routing and logic.
• Security. A custom mask is hard to inspect; an FPGA bitstream lives in external flash and (without encryption) can be intercepted.

The standard rule of thumb: prototype on FPGA, ship on FPGA for volumes under 10K to 100K units, harden to ASIC above that. The definitely-not-esp32 project lives in the FPGA prototype regime: a Tang Nano 20K at ~50 MHz runs an RV32IMC core much slower than the ESP32-C3’s 160 MHz ASIC implementation, which is exactly the expected gap.

FPGA vs CPLD

A complex programmable logic device (CPLD) is the older, simpler cousin of the FPGA. The architectural differences (Wikipedia: CPLD):

• Logic structure. A CPLD uses sum-of-products macrocells (a programmable AND-OR array per cell, like a small PLA), giving fast and predictable two-level logic. An FPGA uses LUT-based logic cells, giving more flexible but routing-dependent timing.
• Capacity. CPLDs scale from hundreds to tens of thousands of logic gates; FPGAs from tens of thousands to many millions.
• Configuration storage. CPLDs use internal flash and boot instantly with no external memory; SRAM-based FPGAs need a separate boot device. (“Unlike many FPGAs, an external configuration ROM is not required.”)
• Timing. CPLD pin-to-pin delays are deterministic to a few nanoseconds; FPGA timing depends on placement and routing.
• Use case. CPLDs win for “glue logic” (address decoders, simple state machines, level translators); FPGAs win for entire systems.

A common pattern is a CPLD on the board that loads the FPGA’s bitstream from flash on power-up, giving the system instant-on behaviour while the FPGA does the heavy lifting. The Tang Nano 20K’s onboard BL616 plays this role (loading the bitstream into the GW2AR’s SRAM over USB or from on-board flash).

Soft Cores

An FPGA can run a CPU in two ways:

• Hard core. A real silicon CPU embedded next to the FPGA fabric, sharing the package. Xilinx Zynq embeds two ARM Cortex-A9s; Intel SoC FPGAs embed ARM Cortex-A53s; Microchip PolarFire SoC embeds five RISC-V U54-MCs. The CPU runs at full ASIC speed (1+ GHz).
• Soft core. A CPU described in HDL and synthesized into the FPGA fabric. Xilinx MicroBlaze, Intel Nios II, Lattice Mico32 are vendor offerings; the open-source RISC-V ecosystem provides VexRiscv, PicoRV32, Ibex, CV32E40P, NEORV32, and many others. Soft cores run at FPGA-fabric speed (50 to 250 MHz typically), but they are infinitely configurable and can be modified, instrumented, and verified at RTL.

The definitely-not-esp32 core is a soft core, written from scratch, synthesized to the Tang Nano 20K’s GW2AR-18 fabric. The CPU runs slower than an ESP32-C3 by definition (FPGA fabric is slower than ASIC silicon), but the project ships the RTL the user controls, which is the entire point.

Small, Hobbyist FPGAs and What They Cost

The under-$50 FPGA market exploded in the late 2010s as Chinese vendors entered:

• Lattice iCE40 series. The iCE40-HX1K through HX8K family was the first FPGA with a fully open-source toolchain (Project IceStorm by Clifford Wolf, the Yosys and nextpnr creator). Boards like the iCEBreaker and TinyFPGA BX retail for $30to$80.
• Lattice ECP5. A larger device (12K to 85K LUTs) with open tooling. The OrangeCrab and ULX3S boards target this part at the $100to$200 range.
• Gowin LittleBee and Arora. Sipeed’s Tang Nano series uses these: Tang Nano 9K (Gowin GW1NR-9, listed at USD 14.90 on Seeed Studio as of 2026-08-08) and Tang Nano 20K (Gowin GW2AR-18, roughly USD 25 to 40 depending on vendor, region, and whether headers are pre-soldered — see the pricing callout below; Sipeed wiki, CNX Software 2023 cites “$25 and up on Aliexpress” at launch).
• Xilinx Spartan-7 / Artix-7. Smaller boards (Digilent CMod S7, $90;DigilentArtyA7,$150 to $300) target student and hobbyist work in the Xilinx ecosystem.
• Microchip PolarFire / IGLOO. Less common in hobby use but provide flash-based, low-power options.

The Tang Nano 20K is a particularly good fit for an RV32IMC project because its ~20K LUT4s and 828 Kbits of BRAM are enough for a small core plus a kernel-sized RAM and a UART, while still being cheap enough to break without consequence.

Inherently volatile - dated range, not a single number

There is no single “the price” of a Tang Nano 20K, and there never will be. This is a marketplace-priced hobbyist board with no manufacturer’s list price published anywhere fetchable, so the honest answer is a dated range with its provenance, re-checked when it matters. What was actually established on 2026-08-08:

Evidence	Value	Notes
CNX Software, 2023-05-22	“$25 and up”	launch coverage; still the most-cited figure
sipeed.com product page	no price published	the page is a JavaScript single-page app; curl returns only the shell, and Sipeed exposes no price in any static markup
Seeed Studio catalog search	not stocked	the direct product URL 404s; Seeed’s search index returns the Tang Nano 9K at USD 14.90 but no 20K
Amazon.com ASIN B0GCVH52SK (“Not Welded”)	EUR 33.62	live scrape; Amazon geolocated the request and rendered EUR, so this is a euro-zone price, not a US one
AliExpress (Sipeed’s own storefront channel)	not verifiable by fetch	item pages are JavaScript-rendered and return no price in static HTML; the redirect chain also bounces to region-local hosts

Working figure: USD 25 to 40 as of 2026-08-08, with the low end on AliExpress direct from Shenzhen and the high end on Amazon/eBay resellers who add import handling and markup. Do not quote a single number, and do not treat the 2023 “$25” as current. To re-verify, load sipeed.com/products/tang-nano-20k in a real browser (the SPA renders a buy widget that curl cannot see) rather than fetching it.

See Also

• Tang Nano 20K - the specific FPGA board the project targets
• Verilator - the simulator used before the FPGA build, where most verification happens
• Register-Transfer Level - the abstraction at which FPGA designs are written
• RV32IMC - the ISA that the FPGA soft core implements
• System on a Chip - the broader architectural category
• Computer Architecture MOC