Tang Nano 20K

The Sipeed Tang Nano 20K is a small, inexpensive FPGA development board built around the Gowin GW2AR-LV18QN88C8/I7 (an Arora-family device with 20,736 LUT4 logic cells, 15,552 flip-flops, 46 block-SRAM macros totalling 828 Kbit, 48 18×18 DSP multipliers, and 64 Mbit of SDR SDRAM integrated in-package via SiP) (Sipeed Tang Nano 20K Datasheet v1.3; Gowin GW2AR Series Data Sheet DS226-1.9.1E). The board ships in a 22.55 mm × 54.04 mm form factor with USB-C power and programming, an on-board BL616 microcontroller that handles JTAG, USB-to-UART, and USB-to-SPI bridging, an HDMI connector, a 40-pin RGB LCD FPC connector, a microSD slot, and dual 20-pin DIP headers exposing 34 user-IOs (Sipeed wiki, Tang Nano 20K; Datasheet v1.3). At a typical street price around US $25 - 35 t h e b o a r d ha s b eco m e t h ec an o ni c a l c h e a pR I S C - V so f t cor e t a r g e t f or h o bb y i s t an d a c a d e mi c p r o j ec t s; C N X - S o f tw a r e^{'} s 2023 l a u n c h co v er a g ec a l l e d i tt h e "$ 25 Sipeed Tang Nano 20K FPGA board” that “can simulate a RISC-V core, run Linux, retro games” (CNX-Software, May 2023). The definitely-not-esp32 project targets exactly this board as its FPGA bring-up platform.

Mental Model

A Tang Nano 20K is a single GW2AR-18 FPGA, an in-package 64 Mbit SDR SDRAM, an external 64 Mbit QSPI flash, and a BL616 microcontroller that does everything an FTDI cable would do (plus more), packed onto a 22 × 54 mm board with USB-C in and HDMI out. The BL616 is what makes it a “USB stick” rather than a bare FPGA chip on a breakout: it boots, programs the FPGA over JTAG, presents a USB serial port to the host, and bridges UART/SPI/I²C to any FPGA-side design. The 40-pin LCD connector and 40-pin DIP user-IO headers do double duty as the board’s main expansion. The GW2AR-18 is the R variant of Gowin’s GW2A line (“R” for in-package SDRAM); the GW2A-18 without the R needs an external SDRAM chip and is what the larger Tang Primer 20K uses (Gowin GW2AR DS226 §2 General Description).

flowchart TB
  USB["USB-C 5V"] --> PWR["DC-DC + LDO<br/>(3V3 / 1V0 / VccIO)"]
  PWR --> ALL[all chips]
  USB --> BL616
  subgraph BOARD["Tang Nano 20K board"]
    BL616["BL616 microcontroller<br/>USB→JTAG / UART / SPI / I2C<br/>+ MS5351 clock control"]
    XTAL40["40 MHz XTAL"] --> BL616
    XTAL25["25 MHz XTAL"] --> EX_PLL
    OSC27["27 MHz osc"] --> FPGA
    EX_PLL["MS5351 external PLL<br/>(2 generated clocks)"] --> FPGA
    BL616 -- "JTAG TCK/TMS/TDI/TDO" --> FPGA
    BL616 -- "UART / SPI / I2C" --> FPGA
    FPGA["Gowin GW2AR-LV18QN88<br/>20,736 LUT4 · 15,552 FF<br/>46 BSRAM (828 Kbit) · 41,472 b SSRAM<br/>48 × 18×18 DSP · 2 PLL (QN88 package)"]
    SDRAM_SIP["64 Mbit SDR SDRAM<br/>(System-in-Package)"]
    FPGA <--> SDRAM_SIP
    FLASH["64 Mbit QSPI flash<br/>(bitstream + user data)"]
    FPGA <--> FLASH
    SDCARD["microSD slot"] --> FPGA
    HDMI["HDMI / TMDS connector"] <-- "differential pairs" --- FPGA
    LCDFPC["40-pin RGB LCD<br/>FPC connector"] <--> FPGA
    DIPHDR["2x20 DIP headers<br/>34 user-IOs"] <--> FPGA
    LEDS["6 LEDs + 1 WS2812 RGB"] <-- FPGA
    BTNS["2 user buttons (S1, S2)"] --> FPGA
    AUDIO["MAX98357A PCM amp<br/>+ speaker pads"] <-- FPGA
  end

Block diagram of the Tang Nano 20K, redrawn from the Sipeed datasheet v1.3 Functional Annotation pages. What it shows: the USB-C connector feeds both power and data; the BL616 microcontroller acts as the single I/O front-end (JTAG programmer, USB-to-serial bridge, clock controller). The FPGA proper sits between BL616 (for programming and host bridging), the 64 Mbit in-package SDRAM (the defining feature of the GW2AR variant), an external 64 Mbit QSPI flash holding the bitstream, and a fan of user-facing peripherals: HDMI, RGB-LCD FPC, microSD, 40 GPIO pins, LEDs, buttons, and an audio amp. The insight to take: for a microkernel-on-RISC-V project, the entire chip-side topology of a real embedded system is reproducible here. You get on-package main memory, off-chip flash, a console UART, and GPIO, and the BL616 means a host PC has UART + JTAG access over a single USB-C cable.

The FPGA: GW2AR-LV18QN88C8/I7

The exact part number on the silicon matters and is repeatedly misquoted; the markings on the board (“GW2AR-LV18 QN88C8/I7 2208C NA3K60.00”) confirm it precisely (Sipeed Datasheet v1.3, Appearance Drawing). Decomposing:

GW2AR. Gowin’s GW2A Arora family, R-suffix indicates system-in-package memory (SDR SDRAM, DDR SDRAM, or PSRAM bonded into the same QFN package as the FPGA die) (Gowin GW2AR DS226 §2).
LV. Low-voltage core (1.0 V Vcc), as opposed to standard 1.2 V variants.
18. Approximate logic capacity in thousands of LUT4s. The exact count is 20,736 LUT4 plus 15,552 flip-flops (Gowin GW2AR DS226 Table 2-1).
QN88. QFN-88 package, 10 × 10 mm, 0.4 mm pitch (Gowin GW2AR DS226 Table 2-3). The package bonding directly determines IO count (66 max, 22 user IOs in the QN88) and PLL availability.
C8/I7. Speed grade C8 commercial / I7 industrial. The board page lists both grades as the same hardware; the speed grade affects timing margins, not capability.

Per the GW2AR datasheet Table 2-1, the GW2AR-18 die provides up to four PLLs total (PLLL0, PLLL1, PLLR0, PLLR1), 8 IO banks, and 384 maximum IOs. But the QN88 package only bonds out a subset of pins, so it exposes only two PLLs (PLLL1 and PLLR1) and 66 maximum IOs (Gowin GW2AR DS226 Table 2-2 Note; confirmed by Sipeed Datasheet v1.3 Hardware Overview: “PLLs: 2”). This is a frequent point of confusion: die-level documentation lists “up to 4 PLLs”; the actual board has 2.

The headline numbers from Gowin’s DS226-1.9.1E and the Sipeed datasheet, side by side:

Resource	GW2AR-18 die	QN88 package on Tang Nano 20K
4-input LUTs	20,736	20,736
Flip-flops	15,552	15,552
Shadow SRAM (S-SRAM)	41,472 bits	41,472 bits
Block SRAM macros	46	46
Block SRAM total bits	828 Kbit	828 Kbit
18×18 DSP multipliers	48	48
In-package SDRAM	64 Mbit SDR	64 Mbit SDR (SiP)
PLLs	up to 4	2 (PLLL1 + PLLR1)
Maximum user IOs	384	22 (66 with JTAG repurposed)
Core voltage	1.0 V	1.0 V
Process	55 nm SRAM	55 nm SRAM

The 55 nm process is significant in two ways: it places the GW2AR firmly in the “mature node” hobbyist tier, and combined with the 1.0 V core voltage it gives the device its low static-power characteristic. Practical clock targets for a small soft RISC-V core on this fabric are in the 50-75 MHz range without aggressive pipelining (CNX-Software 2023 launch coverage cites the board running an RV32 softcore with retro-game emulation at a comfortable margin).

The Arora family name covers GW2A and GW2AR; per Gowin’s product page, “GW2AR series FPGA products are the first generation of Arora family products, and they are one kind of SIP chip. Compared with GW2A series, the difference is that GW2AR series integrates abundant SDRAM” (Gowin GW2AR DS226 §2; Gowin Arora product page). Architecturally GW2A and GW2AR are the same fabric; only the in-package memory differs. The GW2A series datasheet DS102 is therefore the reference for the logic itself (Gowin GW2A DS102 v2.7.6E, May 2025).

On-Board Memory

The Tang Nano 20K carries three distinct memory devices, each with a specific role:

In-package 64 Mbit SDR SDRAM (8 MiB). The defining feature of the GW2AR-18: an SDR SDRAM die bonded into the same QFN-88 package as the FPGA die, with the SDRAM’s address/data/control lines routed directly to internal die-to-die wires (DSRAM bits, 64M per the DS226 table). The board does not expose these pins externally; they belong to the package. From the FPGA logic side, the SDRAM is reached through a Gowin-provided controller IP (or a user-written one), giving roughly 100 MB/s of sequential bandwidth at 100 MHz SDR. For a RISC-V SoC this is the natural place to hold the kernel and user heap once the design grows beyond what fits in on-chip BSRAM.
External 64 Mbit QSPI flash (8 MiB). Holds the FPGA configuration bitstream that loads on power-up, plus user data that the design wants persistent. The BL616 microcontroller can program the flash from the USB host without needing a separate JTAG dongle.
On-chip BSRAM (828 Kbit = 103.5 KiB across 46 macros). The lowest-latency memory, accessible in a single cycle from the FPGA logic. Used for boot ROM, kernel-private data, register files for soft cores, and small caches. This is where the kernel of a definitely-not-esp32-class project lives during early bring-up before the SDRAM controller is brought online.

The BL616 Microcontroller

The BL616 is a Bouffalo Lab RISC-V microcontroller (the same chip family that powers the Pine64 BL602 Wi-Fi modules). On the Tang Nano 20K it serves as the sole on-board USB front-end: USB-to-JTAG for FPGA programming, USB-to-UART for the console, USB-to-SPI for flash programming, USB-to-I²C, plus control of the on-board MS5351 clock generator (Sipeed Datasheet v1.3 Hardware Overview). The Sipeed wiki summarizes the BL616’s role identically: “Onboard BL616, provides USB to UART, I2C, SPI and JTAG” (Sipeed wiki).

There is no separate FT2232 / FT232H / RV-Debugger / CMSIS-DAP probe on the Tang Nano 20K. The BL616 alone covers what those would provide. This is a meaningful cost reduction: a comparable Xilinx hobbyist board with an FT2232 commands a $30 p r e mi u m o v er t h e ba r e F P G A c hi p . S i p ee d^{'} sc h o i ce t o u se t h e B L 616 (a c hi pt h ey l ik e l y f ab r i c a t eor co - d es i g n) i s p a r t o f w h y t h e T an g N an o 20 K hi t s i t ss u b -$ 30 street price.

Connectors and Peripherals

The board’s I/O surface is dense for its size:

USB-C for power, JTAG, UART, SPI, and I²C (all via BL616 bridging). 5 V at up to 0.5 A nominal (Sipeed Datasheet v1.3 Working Conditions).
HDMI / TMDS connector. The FPGA fabric drives differential TMDS pairs (Transition-Minimized Differential Signaling) to a standard HDMI-A connector, supporting DVI-compatible video out at common resolutions (480p, 720p, 1080p with careful pipelining). The reference design uses the 27 MHz on-board oscillator as the TMDS pixel clock source.
40-pin RGB LCD FPC connector. A standard RGB-parallel LCD interface (HSYNC/VSYNC/DE/clock plus 24 data bits), suitable for the LCD modules Sipeed ships separately for the “retro-games” target. The connector pin 1 must align with the cable pin 1 (Sipeed Datasheet v1.3 Precautions).
microSD card slot, addressable from the FPGA fabric for mass storage (a typical use: holding ROM images for emulators, or holding a userland for a softcore Linux).
Two 20-pin 2.54 mm DIP pin headers (40 pins total) flanking the long sides of the board, exposing 34 free I/Os alongside power and ground pins. These are the primary user-expansion headers, breadboard-compatible.
Six on-board LEDs plus one WS2812 RGB LED, useful for blink-bringup and status indication.
Two user buttons (S1, S2) wired directly to FPGA pins.
MAX98357A PCM audio amplifier with speaker pads, driven from the FPGA via I²S.
JTAG test points (TMS/TCK/TDI/TDO labelled on the top silkscreen) for use with an external debugger if the BL616 USB path is unavailable.
External MS5351 PLL providing two additional precise clocks beyond what the FPGA’s internal PLLs synthesise; the 25 MHz reference XTAL feeds it.

Toolchain: Gowin EDA vs the Open-Source Stack

There are two software paths from Verilog to bitstream for this board.

The vendor flow (Gowin EDA). Gowin Semiconductor ships a free closed-source IDE (“Gowin IDE”, or “Gowin EDA Education Edition” for hobbyists). It bundles Gowin Synthesis (synthesizer), the placer/router, the bitstream generator (producing .fs files), and the programmer (which talks to the BL616 over USB or to JTAG dongles directly). Sipeed’s datasheet specifies “Gowin IDE (Version > 1.9.8); Supports Gowin Synthesis” (Sipeed Datasheet v1.3 Software Overview). The vendor flow has the official timing models, full primitive coverage (DSP slices, BSRAM modes, IODELAY, hardened LVDS), and is what any Gowin reference design assumes. Closed-source, occasionally Windows-first, occasionally annoying about licensing keys, but unambiguously functional.

The open-source flow (Yosys + nextpnr-himbaechel + Apicula + openFPGALoader). A bitstream-compatible reimplementation built up over the past several years through reverse engineering. The components:

Yosys handles synthesis (Verilog/SystemVerilog → generic netlist → Gowin primitives via a gw2a-family pass). For the Tang Nano 20K, “you need to call yosys with the chip family” using a -family gw2a flag (YosysHQ/apicula README).
nextpnr-himbaechel is the modern Gowin-capable place-and-route backend, replacing the older nextpnr-gowin. Per multiple recent build guides, “as of November 2024, ‘nextpnr-himbaechel’ had better Gowin 2A family support than ‘nextpnr-gowin’, so it’s recommended to use ‘nextpnr-himbaechel’ instead” (cjacker/opensource-toolchain-fpga; pera’s blog, October 2024). The nextpnr README confirms: “Gowin (LittleBee and Aurora V devices) via Project Apicula” is one of the supported himbaechel-uarch backends (YosysHQ/nextpnr README).
Project Apicula (Python package name apycula) is the reverse-engineered bitstream documentation and the toolchain piece that turns nextpnr’s placed-and-routed netlist into a Gowin .fs bitstream. The PyPI page lists “Apycula 0.32” as the latest release as of April 2026, with 54 prior releases reflecting steady maintenance (Apycula on PyPI; YosysHQ/apicula GitHub). Tang Nano 20K is listed explicitly as one of the supported boards (GW2AR-LV18QN88C8/I7).
openFPGALoader programs the bitstream onto the board via the BL616’s JTAG-over-USB.

The Hackaday writeup from June 2022 captures the state-of-the-art at the time: the Tang Nano 1K / 4K / 9K were the first Gowin parts supported by the open flow, with the 20K following shortly after (Hackaday, June 2022). As of mid-2026 the open flow handles the Tang Nano 20K reliably for designs that stay within the documented Apicula coverage (LUT4, FF, BSRAM, IO, basic DSP, simple PLL modes). Designs that touch the hardened SDRAM controller, exotic IODELAY, or aggressive DSP cascading still need the vendor flow; the gap is narrowing every release.

For the definitely-not-esp32 project the implication is concrete: a from-scratch RV32IMC core that uses BSRAM, a UART, and a Wishbone bus to the SDRAM (via a hand-written SDR controller) fits the open-flow envelope and can be reproduced by anyone with Yosys, nextpnr-himbaechel, Apicula, and openFPGALoader. Vendor IP is unnecessary, which matches the project’s open-source-only spirit.

How the Open Flow Looks in Practice

A complete build from Verilog to a flashed bitstream on a Tang Nano 20K, using the open toolchain:

# 1. Synthesise: Verilog → generic netlist → Gowin primitives
yosys -p "read_verilog top.v; \
          synth_gowin -family gw2a -top top -json top.json"
 
# 2. Place and route for the specific board
nextpnr-himbaechel \
    --device GW2AR-LV18QN88C8/I7 \
    --vopt family=GW2A-18C \
    --vopt cst=tangnano20k.cst \
    --json top.json \
    --write top_pnr.json
 
# 3. Generate the Gowin bitstream
gowin_pack -d GW2A-18C -o top.fs top_pnr.json
 
# 4. Flash to the FPGA over USB
openFPGALoader -b tangnano20k top.fs

Line-by-line: Yosys reads the Verilog and runs the synth_gowin pass with -family gw2a so it emits the right primitives for the Arora family (not the LittleBee family that GW1N targets). The result is a JSON netlist. nextpnr-himbaechel takes the netlist plus a constraint file (.cst) that pins FPGA signals to specific package pins (the IO mapping is read from Sipeed’s published pinout). It runs simulated annealing for placement and a routing search, producing a placed-and-routed JSON. gowin_pack (from the Apicula toolset) converts that JSON to a .fs bitstream in Gowin’s native format. Finally openFPGALoader finds the BL616 over USB and writes the bitstream into the FPGA’s SRAM configuration memory (volatile; lost on power off) or into the on-board QSPI flash (persistent). The whole flow runs in seconds to maybe a couple of minutes for a small design like a basic RV32IMC core; this is what makes FPGA prototyping a tractable inner loop.

Why It’s the Canonical Cheap RISC-V Softcore Target

The Tang Nano 20K hits a particular sweet spot that no other board in 2026 quite matches at the same price:

Enough logic for a real soft CPU. 20K LUT4s comfortably hosts an RV32IMC core (e.g. VexRiscv at ~2K LUTs, PicoRV32 at ~1.5K LUTs, Ibex at ~3K LUTs, or a hand-written 5-stage core at ~5K LUTs) plus caches, peripherals, and a UART, leaving headroom for vision or audio accelerators.
Enough on-chip memory for a small kernel. 828 Kbit of BSRAM holds a 32 KB boot ROM plus a few-tens-of-KB of kernel RAM with room to spare.
In-package SDRAM for the user heap. 8 MiB is enough to run real workloads (an emulator, a network stack, a small Linux in some configurations) without an external memory board.
HDMI out and an LCD connector so a graphical workload (NES emulator, terminal emulator, video pipeline) can be demonstrated without buying more parts.
A real toolchain choice. Both Gowin’s vendor IDE and a fully open flow work today; users can pick based on philosophy.
A street price around $25-35. Sipeed sells direct, Seeed Studio carries it, and Amazon listings track within a few dollars of the Sipeed price.

It also has trade-offs worth knowing. The 1.0 V core voltage and 55 nm process cap effective clock speed; comfortable softcore designs target 50-75 MHz, with serious pipelining and effort required to push toward 100 MHz. The QFN-88 package has only 22 user IOs (66 with JTAG repurposed), which limits how many off-board peripherals can attach simultaneously. The single-debugger BL616 doubles as the only UART path, so simultaneous JTAG-debugging and console I/O requires careful host-side multiplexing. None of these are dealbreakers for a project of definitely-not-esp32’s size, but they shape the design space.

Sipeed sells the Tang Nano family across several FPGA capacities:

Tang Nano (1K). Gowin GW1N-LV1, smallest LittleBee, ~$5. For LED blinkers and intro digital logic; far too small for a soft CPU.
Tang Nano 4K. Gowin GW1NSR-LV4C, ~$15. Has an embedded ARM Cortex-M3 hard core alongside the fabric; useful for hybrid designs.
Tang Nano 9K. Gowin GW1NR-LV9, ~$20. Enough for a small soft RISC-V; was the canonical hobbyist target before the 20K launched.
Tang Nano 20K. this note.
Tang Primer 20K. Gowin GW2A-LV18PG256C8/I7. Same logic family as the Nano 20K but in a PBGA-256 package, exposing 192 IOs and 4 PLLs at the cost of board size and price. Critically the Primer is GW2A (not GW2AR), so the SDRAM is external rather than in-package.
Tang Mega 138K. Gowin GW5A-LV138, much larger Arora-V family device, ~$70-100. Where you go when 20K LUTs is no longer enough.

The architectural transition from Tang Nano 9K (GW1NR LittleBee) to Tang Nano 20K (GW2AR Arora) is also a change of internal LUT family: the LittleBee uses 4-input LUTs grouped in older slices, while Arora uses the same LUT4 but in the larger and faster Configurable Function Unit (CFU) array. Most user code does not care, but timing closure can shift meaningfully between the two.

Production Notes

Sipeed’s own example repository at sipeed/TangNano-20K-example ships reference designs for the LCD, the HDMI output, retro-game cores (Famicom, GameBoy), and a minimal RV32 softcore bringup. These are the primary source for board-specific constraint files.
The board hits its design tradeoffs in the embedded retro-emulation niche: a Famicom (NES) emulator soft core, a tile-rendering display path, audio out via the MAX98357A amp, and controller input via the user-IO headers all fit comfortably on this single board. Sipeed’s own positioning calls out “Special Design for Retro-Games (Optional)” in the datasheet (Sipeed Datasheet v1.3).
For RISC-V softcore development specifically, the open-source community has published several Tang Nano 20K bringups: VexRiscv on the 20K with HDMI text terminal, PicoRV32 with UART boot, and a Linux-capable VexRiscv-SMP variant exercising the in-package SDRAM. CNX-Software’s May 2023 launch coverage notes “can simulate a RISC-V core, run Linux, retro games” precisely because all three are demonstrated within the published board ecosystem (CNX-Software 2023).
For the definitely-not-esp32 project specifically, the Tang Nano 20K is the FPGA phase target. The microkernel and SoC are first developed and verified in Verilator simulation; the synthesis target is the QN88 package with the 2 PLLs (used for the CPU clock and a separate UART baud-rate clock), 30+ user IOs (UART RX/TX plus a small set of GPIO LEDs and buttons), the BSRAM holding boot ROM and kernel state, and the in-package SDRAM holding user-process memory once Phase 6 of the build adds an SDR controller. The board’s small price tag means a busted bitstream or a mis-pinned SDRAM cable is a learning opportunity, not a thousand-dollar setback.

vault

Explorer

Tang Nano 20K

Tang Nano 20K

Mental Model

The FPGA: GW2AR-LV18QN88C8/I7

On-Board Memory

The BL616 Microcontroller

Connectors and Peripherals

Toolchain: Gowin EDA vs the Open-Source Stack

How the Open Flow Looks in Practice

Why It’s the Canonical Cheap RISC-V Softcore Target

Production Notes

See Also

Graph View

Table of Contents

Backlinks

vault

Explorer

Tang Nano 20K

Tang Nano 20K

Mental Model

The FPGA: GW2AR-LV18QN88C8/I7

On-Board Memory

The BL616 Microcontroller

Connectors and Peripherals

Toolchain: Gowin EDA vs the Open-Source Stack

How the Open Flow Looks in Practice

Why It’s the Canonical Cheap RISC-V Softcore Target

Related and Sibling Boards

Production Notes

See Also

Graph View

Table of Contents

Backlinks